The present invention is related to general purpose digital computer systems, and is more particularly related to a prefetch circuit and associated method for operation with a virtual command emulator.
With the advent of microprocessor based integrated circuit chips, many data processing tasks have been assigned to these chips which were previously done by the central processor of a computer system. Microprocessor emulator chips have been developed which include on-chip microcode programs for emulating mainframe instruction sets. In order to emulate a mainframe instruction, the emulator must fetch a command from the memory of the computer system, decode the command into its object instruction code and index registers, as appropriate, and fetch the contents of the index registers before the command is emulated. It will thus be understood that significant time must be spent fetching data from memory before the emulator may begin emulating a mainframe instruction.
U.S. Pat. No. 4,514,803 issued Apr. 30, 1985 to Agnew et al. for "Methods For Partitioning Mainframe Instruction Sets to Implement Microprocessor Based Emulation Thereof" discloses methods of emulating mainframe instruction sets with microprocessor based integrated circuit chips.
U.S. Pat. No. 3,723,976 issued Mar. 27, 1973 to Alvarez et al. for "Memory System with Logical and Real Addressing" discloses a memory system including a cache buffer and means for translating logical addresses to real addresses.
U.S. Pat. No. 4,084,230 issued Apr. 11, 1978 to Matick for "Hybrid Semiconductor Memory with On-Chip Associative Page Addressing, Page Replacement and Control" discloses a means for translating virtual page addresses to real addresses.
U.S. application Ser. No. 643,512 filed Aug. 23, 1984 by Schmidt et al. for "Direct Execution of Software on Microprogrammable Hardware" and owned by the assignee of the present invention, discloses a prefetch circuit which prefetches from a memory location which is a designated number of words displaced from the memory location of the last fetch, and which prevents the attempted crossing of a virtual page boundary during a prefetch operation.